The present specification generally relates to analog-to-digital converters (ADCs) and particularly to differential non-linearity corrections in ADCs using a look-up table.
Analog-to-digital converters (ADCs) employ a variety of different circuit techniques to implement the conversion function. One of the popular techniques used for moderate to high-speed application is the successive-approximation type ADC shown in FIG. 1.
The operation of this ADC is analogous to weighing an unknown object on a laboratory balance scale as 1, xc2xd, xc2xc, xe2x85x9, . . . 1/n standard weight units. The largest weight is placed on the balance pan first; if it does not tip, the weight is left on and the next largest weight is added. If the balance does tip, the weight is removed and the next one added. The same procedure is used for the next largest weight and so on down to the smallest. After the n-th standard weight has been tried and a decision made, the weighing is finished. The total of the standard weights remaining on the balance is the closest possible approximation to the unknown weight.
In the ADC illustrated in FIG. 1, a successive-approximation register 100 controls the digital-to-analog converter (DAC) 102 by implementing the weighing logic with successively smaller size capacitors. However, even though the capacitors are scaled relative to one another, there are often errors in the scaling. A differential non-linearity (DNL) can occur based on errors in the relationship of the sizes and capacities of the capacitors.
An array of ADCs are used in digital imaging devices, such as active pixel sensor (APS) cameras, include many sensors arranged into arrays of columns and rows. Each image sensor collects electrical charge when exposed to light. Control signals provided to the image sensors periodically enable the sensors to transfer the collected charges to the array of ADCs. The collected charges are converted to digital data and stored in the column-parallel ADC registers.
The inventor noticed that by selecting an ADC with a highest number of missed codes for use in generating a look-up table, the response of the ADC can be corrected to have substantially linear response for all the ADCs in an array. Furthermore, the switching on and off of the mismatched capacitors of the successive-approximation ADC causes the missing codes to occur at multiples of power of two. Therefore, the DNL corrections are needed at the same code values for all ADCs in the array. The difference among the DNL behaviors of all ADCs includes the magnitudes of the required DNL corrections.
In one aspect, the present disclosure involves generation of a single look-up table for performing DNL correction on an array of ADCs. Initially, the analog input voltages to the array of ADCs are generated. The input voltages ramp up in steps of some predetermined value. Then, the digital output data are collected and stored in a frame-grabber buffer. A frame of output data are examined for missed codes. The missed codes are identified and recorded. Next, an ADC with a highest number of missed codes is selected for use in generating the look-up table.
The look-up table entries are filled in with consecutive integer values using the corresponding actual output of the selected ADC as an address in the look-up table. During this process, there will be some entries that are missing. These empty entries are filled in with values identical to the value following the empty entries.
In another aspect, a computer-implemented process for generating a look-up table that performs non-linearity corrections on an array of ADCs is disclosed.
In a further aspect, a digital imaging system is disclosed. The imaging system includes a pixel sensor array, a row-select element, and an ADC system. The pixel sensor array is arranged in an array of rows and columns. The sensor array is configured to form an electrical representation of an image being sensed. The row-select element selects a row of pixel sensors to convert. Finally, the ADC system converts electrical charges sensed by the row of pixel sensors to digital pixel data.
The ADC system includes a look-up table and an array of ADCs. The look-up table has an address for each step value of the code and a corresponding entry for the address. The array of ADCs is configured to receive analog voltages from the row of pixel sensors and to convert the analog voltages to the digital pixel data. The conversion is performed by referencing the ADC output to the address in the look-up table and placing the corresponding entry as the digital pixel data on a bus output port.
In some embodiments, the digital imaging system also includes an image display device that is connected to the ADC system. The display device has a display screen and is configured to transfer digital pixel data from the bus output port. The display device arranges the pixel data in sequential order of rows to display the visual image on the display screen.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other embodiments and advantages will become apparent from the following description and drawings, and from the claims.